SOC Pre-Silicon Verification Engineer

• Develops the logic design, register transfer level (RTL) coding, simulation.

• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC.

• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).

• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.

• Reviews the verification plan and drives verification of the design to achieve desired architecture and microarchitecture specifications.

• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

• Integrates blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.

• Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.

• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

We are looking for B. Eng or M. Eng in Electronics, Computer or Electrical Engineering graduates who are recent graduates or have 1-4 years of digital design exposure and experience.

• Job Working experience in verification and integration activities including but not limited to test-plan development, test writing, debug, integration and familiar with verification methodologies such as OVM, UVM or VMM.

• Enjoy pick up protocol knowledge in I/O specifications such as USB2, USB3, SATA, PCIe.

• Genuine curiosity into microprocessors, computer system architecture and high speed design as well as producer consumer transactions.

• Also dedicated and proficient in digital state machine architecture and logic design.

• Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows